Block Constraints Budgeting in Timing-Driven Hierarchical Flow

In this paper, we introduce a new block budgeting algorithm that speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, block budgeting challenges are detailed. Then, we explain why existing budgeting approaches are not adapted to fulfil these challenges. A new block budgeting algorithm is proposed. In order to derive relevant block constraints, this algorithm analyzes the design flexibility. This Flexibility Aware Budgeting (FAB) approach is then compared to some previous ones. Experiments based on commercial EDA tools and real designs show up to 55 % reduction in hierarchical flow run time and lead to a good flow timing closure. I. BLOCK BUDGETING CHALLENGES Any physical synthesis solution has limitations on the size of circuits that can be handled in a single run. “Divide and Conquer” approaches have been introduced to overcome these limitations. In this kind of approach, large designs are sub-divided into smaller synthesizable sub-blocks. Fig. 1 depicts a typical timing-driven hierarchical flow. This flow starts with RTL synthesis and technology mapping. Resulting netlist is assumed to be too big or too complex to meet the specified performance. Thus, the design is partitioned into sub-blocks. These blocks are floorplanned upon the chip die. In fact, the floorplanning step includes design physical partitioning, blocks placement and inter-block net global routing. Then, blocks are optimized. Let’s notice that partitioning technique not only permits to implement large designs, but also allows optimizing blocks concurrently, that can be precious to decrease time to market – this represents one more reason to use the hierarchical flow. Optimized blocks are reassembled at the top-level and top optimization is run. If chip constraints are not met, the whole process can be repeated. To implement sub-blocks, EDA tools need constraints. Blocks constraints are computed by the block budgeting step. The budgeting step derives blocks IO constraints from the chip constraints. In order to speed up the hierarchical flow timing closure, the budgeting process has, first to assign feasible blocks constraints, and, second, to ensure that if blocks implementation succeeded, all chip constraints will be met. These two conditions qualify budgets quality. Another key point of block budgeting step stays in its low resources consumption (budgeting that runs slower than flat optimization is not interesting). If various delay budgeting approaches have been proposed to HDL Description Standard cells library